Samle and Hold facility in input configuration of PSoC 3/5 ADCs | Cypress Semiconductor
Samle and Hold facility in input configuration of PSoC 3/5 ADCs
Dear developers ,
This may be very basic. How does one handle sudden level changes in the signal to be digitized by an ADC while it is currently in conversion mode. Does an ADC on the PSoC IC have any inbuilt sample and hold function in its input to maintain a constant input signal level during conversion or does it only have a garbage value when this kind of a situation occurs? please clarify.