Reset Handling for Warp/DP | Cypress Semiconductor
Reset Handling for Warp/DP
in the following snippet of a FSM, which drives the DP, I've get the error
Synchronous and asynchronous events cannot be mixed in a timing control.
always @(posedge clock or /*AS*/next_state or reset) begin
if (reset) begin
state <= STATE_RESET;
state <= next_state;
How are they handled correctly, the resets. I've found nothing in '"Best Practises' about this.