Reducing Code Spread on ADC DelSig Measurements | Cypress Semiconductor
Reducing Code Spread on ADC DelSig Measurements
Im having difficulty reducing the code spread on a simple DC voltage measurement using the Delta Sigma ADC on the PSOC 5 CY8C5588AXI-060 my simple test is outputting the converted codes via UART to my PC to examine the results. DC Voltage measurements are yielding code values with spreads from 50-200 codes!
I have tried passing the results through an FIR Filter, as well as using an external voltage reference and external clock source. I have even tried to use a Bypass decoupling capacitor on the internal voltage reference as the data sheet said this may help. The code spread improves slightly when the FIR filter is used:
ADC Configuration: MultiSample (Turbo), 16 Bit Resolution, 1000 SPS, VSSA - 2.048, Bypass Buffer
Filter Configuration: 1 ksps, 1 Filter Stage, Blackman, Lowpass, 120 Taps, 0.1 kHz, Data Ready Signal on Interrupt Request.
@1.2 V input to the ADC taking 1000 Samples
No Filter, Internal VREF (1.024): 380000 - 38100
Filter, Internal VREF (1.024): 37980 - 38060
Filter, Internal VREF (1.024), External Clock (250 kHz): 38120 - 38180
Filter, Ext Vref (1.024), External Clock (250 kHz) 38120 - 38165
My main issue is that i have no benchmark to compare against! How low is the ADC code spread actually capable of going on a simple measurement such as this? is there an optimal configuration for reducing this?
Thanks for your help!