Pure UDB/DP Timer | Cypress
Pure UDB/DP Timer
is it possible to write a UDB/DP timer? I need a simple down counter which loads it's count value from hardware register (not written by CPU), which is instanciated in verilog and written from other (DP) stage. At zero count a simple hit signal has to be generated.
The DP has to read this external (parallel in) count value and increment them - using this as A0 DP register, which requires write access to the external one. Following the PSoC TRM this seems not to be possible easy. I can get values from ALU back (parallel out) but this must be written back to the external register connected to parallel in. Is this possible? Which other options do I have.
The goal is to have no CPU/DMA intervention!