PSoC5LP DDS dual phase component problem | Cypress Semiconductor
PSoC5LP DDS dual phase component problem
I am working on DDS component which would produce two TTL outputs with phase delay between them (it might be useful for lock-in amplifier later). As starting example I use IQ_DDS example posted by PSoC73 a while ago:
which based on Verilog DDS code.
My dual phase DDS works to some extent (demo project attached), but shows occasional phase flips by 180deg in certain conditions, described below. I suspect that problem in my Verilog code, please advise.
Attached below demo project, screenshots and video: http:/youtu.be/qVU3PoVIUxw
Video shows that output of two outputs is linearly shifted in cyclical forward backward directions. The phase relationship between outputs behaves as expected while phase is increasing, but there are few 180 deg flips when phase is decreasing.