PSoC5 maximum DMA transfer rate from 8-bit parallel port to RAM | Cypress Semiconductor
PSoC5 maximum DMA transfer rate from 8-bit parallel port to RAM
I am new to PSoC5 programming and need help to master its DMA data transfer.
I started a project that requires grabbing parallel port camera frame data at fast speed. The camera has 8-bit parallel port, VSync, HSync and Pixel Clock. Data format is a 8-bit gray-scale. Resolution 320x240 (QVGA).
I started with single channel DMA arrangement. Basic structure is as following:
1. VSync isr resets the line counter and enables HSync interrupt,
2. HSync isr setup the destination line buffer start address in DMA channel, enables DMA and enables DMA done interrupt
3. following rising edge of pixel clock event triggers DMA read from the 8-bit port, write to the destination buffer and increment the destination address
4. DMA channel is set to length of 320
5. DMA done isr increment the line counter, if the line counter reaches the bottom (240), disable further HSync interrupt.
The above process works OK when camera pixel clock is set to 3MHz. The problem is that the above arrangement does not work for high pixel clock such as 4MHz. My project requires the pixel clock to be at least 6MHz.
Has anybody done the similar DMA? I would like to know if the 3MHz is indeed the DMA data transfer rate limit? If so, will a 8bit -16bit/32bit UDB buffer can help the overall data transfer rate? How such a UDB buffer can be created.