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PSoC5 maximum DMA transfer rate from 8-bit parallel port to RAM | Cypress Semiconductor

PSoC5 maximum DMA transfer rate from 8-bit parallel port to RAM

Summary: 6 Replies, Latest post by hli on 11 Oct 2016 01:16 AM PDT
Verified Answers: 1
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Jianling Weng's picture
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I am new to PSoC5 programming and need help to master its DMA data transfer.

I started a project that requires grabbing parallel port camera frame data at fast speed. The camera has 8-bit parallel port, VSync, HSync and Pixel Clock.  Data format is a 8-bit gray-scale. Resolution 320x240 (QVGA).

I started with single channel DMA arrangement. Basic structure is as following:

1. VSync isr resets the line counter and enables HSync interrupt,

2. HSync isr setup the destination line buffer start address in DMA channel, enables DMA and enables DMA done interrupt

3. following rising edge of pixel clock event triggers DMA read from the 8-bit port, write to the destination buffer and increment the destination address

4. DMA channel is set to length of 320

5. DMA done isr increment the line counter, if the line counter reaches the bottom (240), disable further HSync interrupt.

The above process works OK when camera pixel clock is set to 3MHz. The problem is that the above arrangement does not work for high pixel clock such as 4MHz. My project requires the pixel clock to be at least 6MHz.

Has anybody done the similar DMA? I would like to know if the 3MHz is indeed the DMA data transfer rate limit? If so, will a 8bit -16bit/32bit UDB buffer can help the overall data transfer rate? How such a UDB buffer can be created.

Thank you!

 

user_342122993's picture
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579 posts

Jianling, You haven't mention CPU clock setting. 8-bit DMA transfer takes ~14 clocs to complete, so at 48 MHz transfer rate will max out at ~3 MHz.

For 16-bit transfer take a look on FIFOin component from PSoC Sensei library:

8-bit / 16-bit FIFOin example (updated by KeerthiRocks):

http://www.cypress.com/forum/psoc-5-architecture/fifo-sample-8-or-16-bit...

 

 

Post your project to have deeper feedback.

Jianling Weng's picture
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3 posts

thank you for the good point. After I changed the both pll output and master clock from 24MHz to 48MHz, the DMA seems can finish the data transfer when pixel clock is at 6MHz now. I will continue verify the memory content as next step.

user_342122993's picture
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579 posts

Jianling,
Without knowing the specifics of your code, i suspect that each second byte gets lost. Max amount of 8-bit DMA transfers achievable should be less than 48MHz / 14 = 3.4 MHz. Please let us know the results of testing.

Jianling Weng's picture
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3 posts

Hi Odissey1, 

My test confirmed that the content captured is correct at 6MHz pixel clock.

It is interesting that speed limit seems to be between 6 and 7MHz when the core clock is at 48MHz. Where did you find the information about the 14 cycles DMA transfer needs? Is it possible that DMA read and write can overlap half of their overall cycles? I am curious to this. Thanks again.

user_342122993's picture
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579 posts

I comparing it with SRAM-DMA-VDAC transfer speed (utilized e.g. in WaveDAC), where it takes 14 clocks. My guess the difference comes from external drq trigger processing time (6 clocks for each request). I am further guessing that you have continuous inter-spoke data transfer as SRAM-to-periferial, taking 8 clocks (AN84810 - Advanced DMA topics), which makes max speed 48E+6 / 8 = 6 MHz. But why it works up to 7 MHz (7 clocks) I can't figure yet, need more learning... 

hli
user_78878863's picture
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2575 posts

Please look at the PSoC5LP TRM, part 6.2 (DMA controller).

The cycle time for a DMA transfer is 'N+6' with N=transfer count / spoke width. So it takes 7 cycles to transfer a single byte.

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