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PSoC 5LP (CYC5868AXI-LP35): Using P1[3] as a GPIO | Cypress Semiconductor

PSoC 5LP (CYC5868AXI-LP35): Using P1[3] as a GPIO

Summary: 7 Replies, Latest post by Bob Marlowe on 30 Apr 2015 08:34 AM PDT
Verified Answers: 0
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jfduval's picture
1 post


In the System tab I set Debug Select to SWD (serial wire debug). When I build the project, I get this message: "Note: debugging option SWD has been changed to SWD+SWV in the System design-wide editor.".

It prevents me from using P1[3] as a GPIO.

Why can't I use SWD without SWV? How can I disable that automatic change?





user_14586677's picture
7646 posts

From the TRM here are the fixed assignments -


user_14586677's picture
7646 posts



Regards, Dana.

user_78878863's picture
2553 posts

The PSoC5LP data sheet states that "the SWV trace output is automatically activated whenever SWD is activated". So you can use this pin as GPIO, as long as your hardware doesn't interfere with the SWV capabilities (and can live with the fact that during programming there might be uncontrolled pulses on this pin).

wleo's picture
Cypress Employee
4 posts

It can be used as GPIO. Suspect that you didn't change the option successfully.

Confirmed under Creator 2.2 CP6.

jlangfo5's picture
67 posts

 That's very interesting to me, and I was wondering if that might the answer to one of my questions I was having. Do you know if there are any other pins that have this behavior where they might drive high during normal operation when configured as a GPIO without the progammer explicity driving them?

zafar's picture
1 post


I faced the similar problem, In my project I have selected P1[3] as GPIO but when I made the project as bootlodable automatically the GPIO option got disappeared. 

Any one knows what went wrong.


Thank you.

user_1377889's picture
9294 posts

Welcome in the forum!

Can it be that in your bootloader you switched on SWD. This setting might override your setting in the bootloadable.



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