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PSoC 3/5 Hardware Programming from Bootloader | Cypress

PSoC 3/5 Hardware Programming from Bootloader

Summary: 2 Replies, Latest post by victoraargote on 10 Feb 2010 12:27 AM PST
Verified Answers: 0
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user_26804380's picture
User
26 posts

When using a bootloader to update main program from .hex file generated for psoc creator, how is the hardware(UDB) reprogrammed in PSoC 3/5? Sorry if this is a stupid question but where is the information on TRM about hardware programming for Universal Digital Blocks?

Thanks

yfs
yfs's picture
Cypress Employee
101 posts

When you make designs in PSoC Creator the configuration is really just data that gets linked into the final downloaded image in flash. When the device boots that data gets copied (usually by DMA) into the digital blocks and routing. In a bootloader situation the same is true - twice. You have a "bootloader" design that is programmed into the device normally (i.e. via MiniProg3) and, when it powers up, it initializes the UDBs. If a bootload is required then the host will send a "bootloadable" design, via I2C, which replaces the original and then resets, which boots up and configures the UDBs just as before.

-- mgs

user_26804380's picture
User
26 posts

Thanks that exactly i was needing to know.

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