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Programming PSoC 5LP flash with a SEGGER J-Link | Cypress Semiconductor

Programming PSoC 5LP flash with a SEGGER J-Link

Summary: 1 Reply, Latest post by Bob Marlowe on 21 Feb 2016 01:54 AM PST
Verified Answers: 0
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cyrozap's picture
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I'm having a little trouble programming the flash of the CY8C5888LTI-LP097 on my CY8CKIT-059 with my SEGGER J-Link. Specifically, SPC commands don't seem to do anything. What I would like to know is:

  • Is it absolutely necessary to enter Test mode (writing 0xEA7E30A9 to 0x40050210 within the ~400 microsecond window during startup) to be able to run SPC commands? I was under the impression that Test mode was only meant to ensure that the SWD pins would not be remapped before the debugger could connect to the chip.
  • If Test mode is necessary for device programming, are there any other ways to enter Test mode via SWD other than the ones detailed in the Device Programming Specification? For example, can I make the chip enter test mode with a SYSRESETREQ or does it have to be a "hard" reset from power-cycling or using the reset pin?
  • How is the bootloader able to reprogram the device? Does it use SPC commands or some other method?

My end goal is to write a PSoC 5LP driver for OpenOCD, so I need to find a way to program my PSoC 5LP without a custom programmer, KitProg, or MiniProg3. Currently, it successfully connects to the ARM core and can read and write memory, reset and halt the processor, and can other otherwise interact with the M3 core normally--it's just having trouble with the SPC.

user_1377889's picture
9279 posts

I would suggest you to contact Cypress directly: At top of this page "Design Support -> Create a Support Case".



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