Problem with Digital output timing | Cypress Semiconductor
Problem with Digital output timing
I am working on a project that needs to toggle an "H" Bridge at 125kHz.
If I drive just one output pin on and off I get the exact same ON and OFF period. When I add a second drive pin the ON time gets longer than off time for some reason. I have attached the bundle for the project. It just uses NOPs to create delay for on and off (I am not sure how accuracte the cyDelayus routine is).
If I uncomment NMOS1 only, I get 8us ON time and OFF time. If I comment out NMOS1 and use NMOS2 I also get 8us ON time and 8us OFF time. If I use Both then I get 10.7us ON time and 8us OFF time for BOTH.
The program needs to set P1/ N2 for the first 1/2 cycle and P2/N1 for second half with symettrical 4us period. (During each half cycle it switches off the unused pairs of control)