Peripherals / master clock influence at CPU clock | Cypress Semiconductor
Peripherals / master clock influence at CPU clock
We are new to PSoC, and currently investigating it for a new project, where we need shift registers to clock data in and out.
We compiled the shiftreg example project, changing it to 32 bit wide, and setting master / bus clock to 66MHz.. STA reports setup violation and f max is 53MHz.. Lowering the master / bus clock to 48MHz removes the violation.
According to doc. bus / CPU clock must be equal or lover than master clock ( UDB clock ? ). It looks like the use of UDB's and perhaps other peripherals will put restrictions to the CPU speed ?
Is this really correct, or am i missing something