Logic gate kills clock signal? | Cypress Semiconductor
Logic gate kills clock signal?
I'm trying to synchronize two PWM's using an AND gate and Control Reg. My thought was to set the Control Reg to zero by default, which would null the output of the AND gate. Then, in my main function, after both PWM's are initialized, I would set the Control Reg to 1 and active the AND gate to pass the clock signal through it.
The PWM's work fine without the AND gate. When the AND gate is added, nothing works. I've tried initializing the Control Reg to 1 and the PWM's still do not work.
It seems like a bug, has anyone else experienced this? Can anyone recommend an easy way to synchronized the PWM's?
********* main.c code **********
CY_SET_REG8(CYREG_MLOGIC_DEBUG, CY_GET_REG8(CYREG_MLOGIC_DEBUG) | 0x40);