how to put value to reg or integer for verilog design | Cypress Semiconductor
how to put value to reg or integer for verilog design
I am new on this forum. I would like to develop a component for PSoC5 based on Verilog code. It's the first time I write Verilog code (I use VHDL at school).
I've got problem to put value for integer or reg element.
For example, I would like to write:
Reg [7:0] position=8'10000000;
But I've got this error message:
"Expected , or ;, but got ="
How can I correct it?
Thanks for your help.