How to properly change size of Shift Register's FIFO? | Cypress Semiconductor
How to properly change size of Shift Register's FIFO?
I need to be able to produce a stream of data consisting of 24-bit words with no spacing between them. To achieve that I'm using a Shift Register - I'm writing my data to its FIFO and then enabling the circuit which loads FIFOed data onto the shift register (see the schematic).
Things work of with default FIFO size of 4 (i.e. I can load up to four 24-bit words and they will be produced out of the shift register. If I try to load more things from the FIFO than I put there, garbage comes out). However, changing FIFO size (by altering the #define ShiftReg_1_FIFO_SIZE 4u in ShiftReg_1.h) does not seem to be altering the FIFO's size. What's up with that? If not by modifying the define, how do I change the size of the FIFO? There is nowhere to do it in the components configuration prompt and I haven't been able to find any other place in code.