Frequency Counter, How to reduce UDB | Cypress Semiconductor
Frequency Counter, How to reduce UDB
Summary: 8 Replies, Latest post by DhruvAcharya on 02 Mar 2015 01:26 AM PST
Verified Answers: 0
27 Feb 2015 06:01 AM PST#1
I have implemented Frequency (RPM) measurement using ideas displayed on various thread by Dana. I have attached project. I have two issues now:
1. I want to reduce the usage of UDB as I have four channels of RPM to be measured and many other function needs to implement. I think I will need extra space in UDB. How can I change Counter Block to fixed functions? I have tried it but it says :
Timer "\RPMCounter_1:CounterHW\" can only use one of the digital clock dividers or bus clock as the clock source.
2. See in attached project I have used 12KHz clock to simulate RPM. I have connected external wire link from this RPM_Freq output (P0) to RPMSig_1 input(P0). For 12KHz it displays perfect values on LCD, but for 15KHz it displays ‘zero’ on LCD. If I try to give direct 15KHz on schematic page (as direct clock source internally in silicon, no external link). It perfectly displays Frequency and RPM. Do I missing something here? Will my development work when I connect actual RPM signal (0-50KHz)?