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Frequency conter using Datapath | Cypress Semiconductor

Frequency conter using Datapath

Summary: 2 Replies, Latest post by tommoxon on 10 Sep 2011 06:37 PM PDT
Verified Answers: 0
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user_112722124's picture
1 post

I am trying to evalute if the PSoC 5 chip is the right platform to use.
I wrote a simple verilog state machine that detects if a signal is within
a specified range. The states are:
parameter IDLE  = 2'b00;
parameter COUNT = 2'b01;
parameter JUDGE = 2'b10;
parameter DONE  = 2'b11;

The machine goes from IDLE to COUNT on a rising
edge of the input signal to measure.
From COUNT to JUDGE on a falling edge.
In the JUDGE state it compare the "count" against two constants to see if
the "count" is within range. It then goes to "DONE" and back to "IDLE";
It can go from JUDGE to IDLE since there is nothing being computed at DONE.

The above state machine consumes just about all UDB resources. So after watching the Sensei videos on
Datapath I understood that is much better to use the Datapath for these things.

The input signal to measure is ~100KHz square wave. The input clock the Datapath is 12MHz.
So the intent is to count "Datapath clocks" while the input signal is "high".

So the questions:
1. The video slides says I can compare A0 with D0, but this option is not in the Datapath Config tool.
2. How can the above design be done with the Datapath tool? It should be very simple right? well, I
have not been able to do it.




David Ron's picture
23 posts



A0 can be compared with D1 as is shown in the training video.

there's a video on an 8 bit pwm using datapath. that'll be useful for you to understand the use of comparison of A0 and D1.

user_7880656's picture
49 posts


Writing new components in verilog is somewhat involved, and rarely necessary for a simple state machine.

I would first use a Lookup Table Component, and do it with schematic capture.

It will accomplish what you want without having to manually code a datapath.

best regards,

Tom Moxon


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