You are here

Filters of 18 bits with ADC Delta-Sigma in differential mode. | Cypress Semiconductor

Filters of 18 bits with ADC Delta-Sigma in differential mode.

Summary: 4 Replies, Latest post by JJWarriner on 07 Jan 2013 04:32 PM PST
Verified Answers: 0
Last post
Log in to post new comments.
user_18397477's picture
4 posts

Dear community:

I have been working with ADC Delta-Sigma in differential mode with 18 bits as inputs for a complex filter of 2 stages
(bandpass and stopband). Despite it would be the logical way to use DMA, this can't handle signed numbers, only unsigned.
ADC converts signals in differential mode with outputs in 2's complement, which this make DMA useless for this problem.

So I decide to write directly STAGE_REG with ADC value. I have read there's some considerations for enter values on filter.
I entered right and left justified, without API's functions 'cos they consider unsigned the value, and also the doubt of being
right or left justified values. Everything works fine in single mode, but in differential mode simply doesn't work.

1.- Are there more special considerations to enter and get values for filters?
2.- Is there any application note, technical note ot whatever with ADC D-S in differential mode with more than 8 bits entered
in a complex filter?

Any help you can provide me I really appreciate it. There should be more documentation about this differential mode.
Differential mode with filters is one of the strengths of PSOC5.

Thanks in Advance!!.

JJWarriner's picture
7 posts

Bumping this post.  I have a similar issue I'm working on.

I'm trying to get the following chain to work.  ADC_DelSig(16bit differential)-->(dma)--->DFB_LowPass--->(dma)--->SRAM.

It's driving me insane trying to figure it out.  Any examples or pointers would be greatly appreciated.  

user_14586677's picture
7645 posts
JJWarriner's picture
7 posts

 I know them by heart.

I think I may have figured it out actually.  I found an app note that was partially helpful:  EP58353.  

So a brief explaination of the crucial details:

I have  the following registers settings on the DFB (This was the tricky part for me):  

Filter_COHER_REG = 0x55;

Filter_DALIGN_REG = 0x0F;

I have two DMA's, one to transfer from ADC to DFB, and on to transfer from DFB to SRAM.  Here are the configs and addresses from the two.
ADC to Filter:
    CyDmaTdSetConfiguration(DMA_DelSig_TD[0], 2, DMA_DelSig_TD[0],0);
    CyDmaTdSetAddress(DMA_DelSig_TD[0], LO16((uint32)ADC_DelSig_DEC_SAMP_PTR), LO16((uint32)Filter_STAGEA_PTR));
Filter to SRAM:
    CyDmaTdSetConfiguration(DMA_Filter_TD[0], 2, DMA_Filter_TD[0],TD_INC_DST_ADR);
       CyDmaTdSetAddress(DMA_Filter_TD[0], LO16((uint32)Filter_HOLDA_PTR), LO16((uint32)Filter_Output));
Like I said, it appears to be working now.  I'll need to spend some more time with it to be sure.
I'm a little concerned about the output of the ADC being in 2's complement form and the DFB not handling that.  I have to check to see what the Filter puts out when a negative value comes from the ADC.
JJWarriner's picture
7 posts

 Hooked up a voltage source and swept the range.  Everything looks good.  Thanks for the help.

I would recommend an app note for this for others who may travel down this path.  

Log in to post new comments.