emFile clock setup time violation | Cypress Semiconductor
emFile clock setup time violation
I'm building a PSoC5LP design that includes a microSD card. I've created an emFile module instance (named "uSD") and assigned the pins (to a bank with 3.3V VDDIO).
After adding other stuff to the design, I started getting this warning during the build:
Warning-1366: Setup time violation found in a path from clock ( uSD_Clock_1 ) to clock ( uSD_Clock_1 ).
There's a timing analysis report that indicates an 0.138ns setup time violation for this clock, but I don't understand how to fix it. The only thing I've found that prevents the timing warning is dropping the Master clock from 48MHz to 24MHz. There's nothing in the emFile configuration for setting the clock source (only an SPI frequency setting, which doesn't seem to help). If I try to change uSD_Clock_1 in the .cydwr Clocks tab, it opens a read-only ("can't be saved") diagram emFile_v1_20.cysch, which shows Clock_1 wired to MASTER_CLK/1.
Does this mean I have to run the Master clock at 24MHz to use emFile? Or can I make a copy of the emFile module and modify it to use MASTER_CLK/2?