Dynamic product terms | Cypress Semiconductor
Dynamic product terms
Is it possible to directly alloctate individual PLD blocks within Verilog components, then using the resulting cyfitter mapping from C code to dynamically reprogram the product terms?
Essentially I am looking to compare parallel input signals against an array of test keys, where the routing is fixed but the comparands (and masking) need to be reprogrammed at run-time.
One alternative scheme would be to use an array of time-multiplexed datapaths with parallel inputs. Perhaps the FIFOs can be made to store four key bytes each by cyclically underflowing the buffers. The parallel inputs seem to eat a lot of status cells though.
Unfortunately indexed DMA appears to carry a sufficiently long latency to be impractical for this use unless perhaps the triggers are speculated early. Plus they can't reach the bit-banded SRAM region. A final option might be to spring for a DFB-equipped part and try some form of hash-table comparison against the internal memory there, though I honestly don't know whether this is feasible.
Lastly a disclaimer: I'm still very much new to the PSoC environment and this HDL business in general and so I still only have a faint idea of how to get the most out of these resources. Feel free to suggest any alternative means of achieving the same ends if dynamic PLD components are infeasible.