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Duty Cycle Varies with Frequency of Write | Cypress Semiconductor

Duty Cycle Varies with Frequency of Write

Summary: 0 Replies, Latest post by ifs on 01 Feb 2014 05:44 PM PST
Verified Answers: 0
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user_360583550's picture
4 posts

Hi, I am new to PSoC programming, and I have encountered some confusing
behavior. I have a PSoC5 LP device, and I'm trying to develop a parallel
interface using a port on the device. I began testing my write speed by simply
writing two alternating values on the port: specifically, I wrote 0x40 and 0x01
to the correct register for P6. These values will alternate driving P6_6 high
and P6_0 high. That is, while P6_6 is high, P6_0 is low, and vice versa. If I do
this at a rather slow speed, I get a nice waveform that you'd expect from these
pins, What is strange is that whenever I try to optimize the bus speed and clock
speed to achieve an overall frequency somewhere above ~2MHz, I get a somewhat
deformed duty cycle on both pins. So where before I'd have about a 50% duty
cycle on both pins, now I have about a 33% duty cycle on one pin, and a 66% duty
cycle on the other. Here are some images of the waveforms at the slow and high
speeds, respectively:


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