DMA won't execute transfers when set up properly | Cypress Semiconductor
DMA won't execute transfers when set up properly
I've been using DMA in several projects lately, all working fine after some trial and error, but I'm using a slightly different project and now it won't work.
my DMA reads in the different values from the SPIM component's rx ptr (I have done this several times) but instead of putting them into one array, it separates each 32 bits into 3 different arrays (every 32 bits goes to 1 of the 3 arrays). It does this by using some verilog to multiplex through which DMA the SPIM_rx_INT triggers.
I have verified the verilog component is working properly and with zero delay, but for some reason when I have it inside my project the DMAs do not seem to transfer anything, and the TD done output is never set.
I previously had a similar setup where I had the
SPIM>DMA(3 TDs each with a 32bit value) >verilog to sequence DMAs creating the arrays>3 DMAs to create 32-bit arrays,
and this setup worked just fine, but I wanted to switch my setup around to free up some DMAs and stop wasting time reading/writing from sram.
What I want to have is,
SPIM>verilog to sequence DMAs creating arrays>3 DMAs to create 32-bit arrays.
but the DMAs are not transferring for some reason
I am posting my project here, if someone feels generous I would appreciate it if they could give their input, I am out of ideas for where to look.