dma problem | Cypress Semiconductor
I am repeatedly transmitting an array in sram over uart. It seems to work fine except that when I try to update the array with cpu access I am only able to intermittently get bytes into the array. Is there any type of blocking that can take place if dma is constantly reading from an array? I was under the impression that dma access to sram was clocked in such a way as to be transparent to cpu access. Has anyone else had a similar experience?