DMA with Preemption? | Cypress Semiconductor
DMA with Preemption?
I am working on a project that features samples being moved from the SAR ADC to a circular buffer via DMA in RAM and then from the circular buffer to an output register via DMA in a 2048 byte burst (writing to output register and other digital logic writes to non-vol).I plan on running the bus clock as 12 Mhz and the ADC at 240,000 sps with 12 bit samples encoded into 16 bit words.
I have been doing some testing, and it looks like that while my I am writing the output register with DMA, I am not receiving any more ADC samples in my circular buffer. I have confirmed this by looking at my outputted samples and I see discontinuities in the data that cover approximately the same amount of time it takes for me to write non-vol.
The ADC DMA priority is set to 0, and the output register DMA priority is set to 2, and I have set bit 23 in the PHUB register with the following code.
uint32 *PHUB = CYREG_PHUB_CFG;
*PHUB = *PHUB | (0x01 << 23);
Which according the TRM:
The DMAC supports two different methods to handle the priority: simple priority, and grant allocation fairness algorithm. The priority handling method can be changed by writing to register PHUB.CFG bit “simple_pri” (bit 23).
Simple Priority: This method handles the channels like any normal priority algorithm where high priority channel can interrupt low priority channel
In this case, I would have expected the ADC DMA to have preempted the output register DMA, but this is not the behavior that I observed. Any ideas or sugestions? Once possible solution I have thought about is using the CPU to grab the ADC samples in an ISR, but I don't find that solution particularly attractive.