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DMA with Preemption? | Cypress Semiconductor

DMA with Preemption?

Summary: 3 Replies, Latest post by jlangfo5 on 05 Nov 2015 02:00 PM PST
Verified Answers: 0
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jlangfo5's picture
67 posts

Hey all,

I am working on a project that features samples being moved from the SAR ADC to a circular buffer via DMA in RAM and then from the circular buffer to an output register via DMA in a 2048 byte burst (writing to output register and other digital logic writes to non-vol).I plan on running the bus clock as 12 Mhz and the ADC at 240,000 sps with 12 bit samples encoded into 16 bit words.

I have been doing some testing, and it looks like that while my I am writing the output register with DMA, I am not receiving any more ADC samples in my circular buffer. I have confirmed this by looking at my outputted samples and I see discontinuities in the data that cover approximately the same amount of time it takes for me to write non-vol.

The ADC DMA priority is set to 0, and the output register DMA priority is set to 2, and I have set bit 23 in the PHUB register with the following code.


*PHUB = *PHUB | (0x01 << 23);


Which according the TRM:

The DMAC supports two different methods to handle the priority: simple priority, and grant allocation fairness algorithm. The priority handling method can be changed by writing to register PHUB.CFG bit “simple_pri” (bit 23). 

Simple Priority: This method handles the channels like any normal priority algorithm where high priority channel can interrupt low priority channel

In this case, I would have expected the ADC DMA to have preempted the output register DMA, but this is not the behavior that I observed. Any ideas or sugestions? Once possible solution I have thought about is using the CPU to grab the ADC samples in an ISR, but I don't find that solution particularly attractive.






user_1377889's picture
9274 posts

This is a very complex case, I would suggest to create a support case to have a Cypress engineer answer that. At top of this page "Design Support -> Create a Support Case".




user_78878863's picture
2551 posts

To quote the TRM:

In both the cases, a DMA channel of low priority can be interrupted by a high priority channel only during the source engine phase

So a running DMA transfer cannot be interrupted. My suggestion: configure your DMA so that only single bytes / words are transferred in a single request /burst. That way after each transfer the ADC transfer can get priority.


jlangfo5's picture
67 posts

Well, I know it's not really the solution to the question I had asked in the case someone ran into similar issues, but in my particular use case, the DMA to non-volatile was actually not needed after I had done some optimization to my code. I was able to clean it up to the point were the dma handled the ADC samples and the non-vol write was done by the processor and still meet real time requirements. I would like to revisit this given time.

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