DMA does not work as intended unless I enable address incrementing | Cypress Semiconductor
DMA does not work as intended unless I enable address incrementing
I am working on a project with indexed DMA, where I simulate a simple ROM chip with my Cy8CKIT-059. For that purpose I use two DMA channels with one TD each. The first channel (SetupRead) reads the requested 16-bit memory address from two UDB status registers and copies it into the source address field of the TD of the second channel (Read). When it is done, it triggers the second channel which reads a single byte from flash at the indicated address and outputs it to a UDB control register connected to the data bus pins.
I managed to get it working, but the final stumbling block was entirely unexpected: I had to configure the TD of the first DMA channel to increment the source and destination addresses, otherwise it would write the first source byte into both destination bytes. In other words, the DMA behaves as if it was misaligned.
However, the DMA is moving 2 bytes from 0x40006464 (where I pinned the two UDB status registers) to 0x40007bfc (the source address for the TD of the second channel). Both of these addresses are dword-aligned, so I don't understand why the DMA is behaving this way, and I didn't find the reason in the documentation either. AN84810 explains that this happens for unaligned transfers, but this cannot be the reason here.
The only hint I found so far is in this presentation, which says on page 52:
DMA between peripherals on same spoke limited to 1-byte burst length
This is consistent with what I see, but I don't find where this is explained in an actual AN or datasheet. In fact AN52705 seems to suggest otherwise when it says:
Limit burst count for intra spoke DMA transfers to less than or equal to 16
Does anyone have a better idea what is actually going on here?