DMA Configuration for I2S | Cypress Semiconductor
DMA Configuration for I2S
I've attached my project for perhaps a bit more ease of communication here. The application of the PSOC 5 chip I am using is for the front display panel of an audio tuner.
If you take a look, you will see that I am using four blocks: an SPI Master, and I2S Master, and two DMA blocks. The SPI is driving a panel of LED's, and functions properly. Code concerning the LEDs has been omitted from my main file (main1.c) for ease of use. The I2S reads in data from an SRC, and the WS, bit clock, and data-in are all connected to the appropriate hardware terminals in the .cydwr file.
Now, my trouble lies in processing the data read from the DMA's. I have two functions to set up the left (0) and right (1) channels' DMA configuration, titled I2S0( ) and I2S1( ). They are identical except for the sources, channel and TD names. I wish to store the incoming data in two buffers, L_Buf and R_Buf, where I can process further. However, when I debug (I am using the MiniProg3), and view the buffers in my 'Watch' window, the data that comes through is not as expected; the input to my tuner is a function generator producing a sine wave, and the data coming through in the end has some kind of information loss. The following specs are probably relevant:
Data bits: 16.
Word select period: 32
Audio sampling frequency: 44.1 kHz (comes through the SRC at about 37 kHz)
I am hoping that someone can help me identify what mistakes I am making in my DMA configuration functions; after testing, I feel like this is where the problem is. Yes, I have read the data sheets for all the blocks included in my design, as well as many application notes which concern configuration of DMA's.
Thank you in advance for even taking the time to look, and any genuine input is greatly appreciated.