design algorithmic Delta Sigma ADC with PSoC | Cypress Semiconductor
design algorithmic Delta Sigma ADC with PSoC
I want to create an algorithmic delta sigma ADC as part of a project.
An algorithmic delta sigma ADC is a 1 loop Delta sigma ADC with a S&H unit that enables us
to divide to sampling process to several stages, in each we sample the error of the previous stage.
The error is the analog voltage residue in the integration capacitor after the first stage of A2D conversion, see attached block diagram.
My goal is to implement at least 2 to such ADC's that work in parallal.
As I understand it each ADC require 2 switch capacitors (SC) units, one for the integrator and another for the S/H unit.
Is it possible to implement it with just 1 SC unit?
I'm wondering whether I should use PSOC 1 or PSOC 5.
PSOC 1 has 8 SC blocks but has a maximum clock of 12 MHz.
PSOC 5 has only 4 SC blocks, but has a maximun clock of 80 MHz.
If there isn't a reason to limit the Delta Sigma sampling rate it seems like PSoc 5 is the better choice.
Am I missing anything?
Also, I am un able to find in integrator block, or a switch capacitor block, in PSoC creator 3.0. Any ideas
where I can find one of these?