Debug and Release mode change the PWM Freq. | Cypress Semiconductor
Debug and Release mode change the PWM Freq.
I´m doing a very easy project with the 5LP kit and Creator 3.3, where i need to generate a PWM signal with 10ms period (and a tiny positive duty cycle), no problems if i compile the project in Debug Mode, i see what i expect on the logic analyzer, but if i change the mode to Release i get a 1.28 ms period.
Does Release mode do any optimizations on the code? I'm only starting the PWM Component on the main loop, nothing else. I have not access to an oscilloscope, i guess the logic analyzer is enough for this. Hope this is not a n00b error.
Attached two screenshots and the easy project.
Thanks in advance