CyResetStatus not being updated to reflect Watchdog timeout | Cypress Semiconductor
CyResetStatus not being updated to reflect Watchdog timeout
I have an unusual problem with reading the correct value from the CyResetStatus variable. I start the watchdog and then delay much longer than the alloted time. My system resets and I place a breakpoint on the first line in 'main'. I have a bootloader timeout of 2 seconds, which I assume is called but then resets the micro after the timeout is exceeded and places the program counter back to the application where my breakpoint is at.
I have read several docs that point me to using this variable, but the reset status variable always returns 0xA0? The top most bit is being set in the bootloader I think, but the watchdog timeout bit is never being set. Any ideas?