Counter Confusion | Cypress Semiconductor
I don't want to sleep or save power, but I *do* want to get a very accurate interrupt every second as the basis of my timebase.
I have a Counter (v2.10) in a PSoC5 design. It generates the first interrupt, but never again, as if it's not running continuously.
By configuration is as follows:
Period: 1999999 (shortened to 1999 for testing)
Compare Mode: Software Controlled (I don't care)
Compare Value: 1999999 (I don't care, shortened to 1999 for testing)
Clock Mode: Up Counter
Capture Mode: None
Enable Mode: Software Only
Run Mode: Continuous
Reload Counter: On Reset, On TC
Interrupt; On TC
Inputs and Outputs:
count: 2MHz clock
clock: 5MHz clock
reset: no connection
tc: no connection
comp: no connection
interrupt: connected to "ISR_UPDATE"
In ISR_UPDATE.c CY_ISR() function, I set a flag true. In main program I wait "while" for flag to be true, then set flag false. In debug mode, I hit a breakpoint inside the CY_ISR() function, then I hit a breakpoint after my wait. But when I continue after that, the interrupt never happens again. I am calling the both counter Start() function and ISR_UPDATE_Start().
Why am I never getting the second update?