Counter Compare Status Bit | Cypress Semiconductor
Counter Compare Status Bit
I’m having trouble with the Timer 3.0 (16-bit UDB) for PSoC 5LP.
What is the intended function of the compare bit in the status register?
The datasheet says it’s sticky, so it gets set to 1 when the compare condition goes TRUE, but if the compare condition remains true, does reading the status register clear the bit, or should it remain 1? My problem is that the compare condition is true (I believe), but when I read the status register the CMP bit is false.