CAN rx mailboxes and FIFO linking | Cypress Semiconductor
CAN rx mailboxes and FIFO linking
can someone please explain the FIFO mechanism behind linked CAN rx mailboxes, please?
I already noticed that there is only one interrupt every Xth message, when X is the FIFO size. Does this mean that I have to handle all messages at once in the interrupt and that the complete FIFO will be replaced when the next interrupt occurs?
If yes, this doesn't really feel like a usual FIFO queue where I usually can pop (get and delete) messages from the front end. Am I using it wrong? Is there maybe some example showing how to do it right?
Thanks in advance!