Build a Verilog component | Cypress Semiconductor
Build a Verilog component
Hello all, I want to build a component which will receive data from adc. After receive data it will take avarage of data and send it to an array. Actually it would work like a DMA component. My problem is I don't have any experience with them. There are some examples about verilog but I really need help about part of DMA. Anyone has a example or any note how can I do it and how can I add it on my project.
If this seems so hard or impossible, can you help me about the this process. As I give detail to my project, I am receiving data from ADC and I send them to emfile via DMA. As you understand, my for structure is fully empty. DMA's do all job. But I need to process this data. Process are avarage, min max value etc. Do you have any idea about that.