Allocating 16-bit status/control registers | Cypress Semiconductor
Allocating 16-bit status/control registers
What is the typical way of instantiating pairs of 8-bit status or control registers in order to create 16-bit accessible registers?
The hardware provides 16-bit registers pairs for the purpose (e.g. CYREG_B0_UDB00_01_CTL) however I haven't been able to figure out how to inform the fitter of the constraint that the two registers should be placed into consecutive UDBs.
For datapaths you would do so by tying the chaining signals between them however in this case there is nothing to be chained. Nor do the standard components seem to support allocation of wider registers. Is there perhaps something akin to a "cy_psoc3_control16" component or a special UDB pairing constraint directive?
This is part of the critical innerloop where every cycle counts (hence why it was was off-loaded to hardware in the first place) and so manually combining 8-bit accesses is rather expensive. The workaround would be to force the UDB allocation outright with placement_force directives but naturally I'd prefer letting the optimizer have as free of a reign as possible.