Advice on attempting a parallel design | Cypress Semiconductor
Advice on attempting a parallel design
Disclaimer: I apologize if this question is off-topic but I'm quite new to the field of programmable logic and would like to drawn on your collective experience to help me decide if a PSoC device is the right way to go. I don't mind putting in the work but at this stage I'm lacking intuition about what is feasible and would like to avoid running into icebergs later on.
The project I am attempting is to build a hardware debugger for a recalcitrant microprocessor system. This system has a bus with 8 data + 16 address bits, plus control signals, running at 1 or 2 MHz.
My rough design for the real-time (i.e. hardware assisted) part looks something like this:
- Route the bus to the parallel inputs of four datapaths, capturing each cycle.
- Save the data from each cycle into a cyclic trace buffer via DMA.
- Hash the address with a CRC.
- Mask the checksum and use it to perform indexed DMA into a breakpoint table.
- Compare the retrieved candidate breakpoint against the real addresses, optionally halting the CPU on a match.
In addition this particular MPU cannot be halted at any point. So a state machine needs to sequence through the instruction bytes in lock-step with the MPU, based on the opcode byte. Plus a slew of other details and complications too gnarly to mention.
I don't expect a detailed review but is this the sort of thing a PSoC is suited for or will I quickly hit timing/routing limits? For the record I've managed to build a prototype, around a PSoC5LP, and have sort-of gotten the trace running.