Adding Component Breaks DMA Transfer | Cypress Semiconductor
Adding Component Breaks DMA Transfer
I'm still getting familiar with PSoC 5LP. Hopefully this is a simple question that can be answered with a link to some document I should have read.
The project has a DMA transfer to an SPI Master component. This is a series of 8 bit writes on TX FIFO not full. The transfer normally works fine.
The problem starts when a Quadrature Decoder component is added. I also noticed the same problem with SPI slave, but will refer to the Quadrature decoder for this example. After the Quadrature Decoder is added, the DMA transfer bytes appear to be out of order. This is a result of adding the component, with no manual C code changes.
For example, a byte buffer with consecutive 0 through 15 was set up as the source. The following transfers were observed:
Sequence after adding Quadrature Decoder component:
I don't know how these components could interact. Any ideas on where to start investigating will be appreciated.