ADC_DMA_VDAC | Cypress Semiconductor
I'm trying to implement a project involving an ADC, DMA and VDAC. The incoming voltage is in the form of a sinusoid, lying in the range +- 20mV centered at 0, with a frequnecy of 3KHz. However, when this is input to the ADC (of type Delsig, in differential mode of range +-2.048V with a sampling resoultion of 8 bits), out come of the VDAC (of range 0-4.080V) a voltage of peak 3V. Same is the case when there is 0 input but still the peak 3V out of VDAC. Is this due to the fact that my input peak voltages are very low? The project works fine when my input voltage lies in the range 0-3V. How can I get around it? Thank you!