ADC SAR low SPS issue | Cypress Semiconductor
ADC SAR low SPS issue
I want to run SAR ADC at lower sampling ratio, let say 300 SPS, which is not allowed in the design. I read that there is a way around this using external clock for the SAR. I put a clock at 5400 Hz, and rebuild the project. It automatically put the SPS ratio to 300 and gets the clock of 5.40054 kHz. But there is a flashing red exclamation mark in the field with the clock in the component window. It says that accepts between 1MHz and 18MHz clock frequency only (the thing that I want to go around), but with that frequency I cannot get a low SPS. And I need 2 SARs to work in parallel getting signals from 2 different analog inputs. Nevertheless the project could be build without errors. So, is that an issue, or I should not pay attention to it. If this is a problem, why compiler (clean and rebuild option) does not catch it, and if it is not an issue, why do I have the error?