ADC DelSig real sampling time | Cypress Semiconductor
ADC DelSig real sampling time
I am trying to do a project similar to this one: Hardware Multiplexing of SAR ADC – PSoC® 5 - EP64560 (http://www.cypress.com/?docID=34834). But only with the ADC DelSig.
In the Datasheet there is a passage on page 6 where the switching timing is explained:
"The SAR ADC is configured for 8-bit resolution and in continuous mode operation. A 14-MHz clock is given to clock input of the SAR ADC. It takes 14 clock cycles for each conversion resulting in conversion rate of one Msps.
It samples the input for four clock cycles. The number of cycles for sampling is configurable in register ADC_SAR_SAR_CSR2_REG. The default number of cycles for sampling is four. After sampling, it converts the signal from analog to digital for next 10 clock cycles. During these ten clock cycles, the input is not being used by the ADC and channel is switched during this time."
My question is:
Where can I find the number of cycles for sampling for the ADC DelSig.
I've searched the PSoC® 5 Registers TRM, but I couldn't find anything like this.