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36 Phase PWM control | Cypress Semiconductor

36 Phase PWM control

Summary: 6 Replies, Latest post by odissey1 on 01 Sep 2016 09:41 AM PDT
Verified Answers: 2
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pcf1ru_1652016's picture
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Hello 
For my current project i need 36x phase PWM  output Up to ~100khz  each , with phase shift , and dead time  control .
Whether implementation of this project is possible using Psock5 , with use of any existing components. ?

user_342122993's picture
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user_1377889's picture
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10106 posts

Assuming that each of the PWMs is consuming one UDB you will be able to implement in hardware as a max 24 PWMs.

At frequencies up to 100kHz even a software implementation could be too tight to CPU limits. Think of using 2 PSoC5 chips.

 

Bob

implicit's picture
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28 posts

I presume you'd run them at the same frequency given the phase-shift requirement?

If so then continually generating a static signal would involves 72x toggles at some cycle and order within one period, continually repeating the same pattern. This pattern might be played back from a pre-assembled buffer through an array of UDB FIFOs with parallel outputs routed to the pins. Say with 36-bits of pin data and a cycle count defining when to trigger the next edge in each DMA word using a separate counter.

Then you could pre-compile such scripts in software, including a transitional buffer to handle the crossover, which would be swapped over with DMA transaction chains once submitted. Effectively modification would be relatively CPU intensive (sorting the flank events, etc) this work could be performed entirely asynchronously and so wouldn't be critical unless you require fast and continuous modification of the waveforms.

Of course even then the compilation algorithm might be optimized to perform single-cycle parameter shifts efficiently, probably not even requiring the transitional buffer.

edit: At maximum resolution DMA bandwidth may be a problem for short pulses in rapid succession. You might want to use an absolute cycle comparator instead of a relative delay to re-synchronize after a quick pulse train draining the FIFOs. Perhaps juggle both UDB FIFOs for extra tolerance.

user_342122993's picture
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675 posts

pcf1ru,

your question is ambiguous. Can you please specify how many PWM blocs you need and what relative phase granularity you expect for each one? How far phase shift would go (is 0-90 deg enough or 0-360deg)? Bit resolution, etc...

pcf1ru_1652016's picture
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2 posts

Thanks  All!!
36x PWM  for control 36x Phase motor
360deg  16 bit phase shift
8bit Duty
frequency up to 100khz 
 

user_342122993's picture
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675 posts

pcf1ru,
it looks like you need single 36-phase 16-bit PWM component, which is outside of PSoC hardware resources. This is trivial task for small $20 FPGA though.

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