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Writing a series of booleans into UDB FIFO? | Cypress Semiconductor

Writing a series of booleans into UDB FIFO?

Summary: 2 Replies, Latest post by on 07 Jun 2016 11:50 AM PDT
Verified Answers: 1
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I'm using the datapath with FIFO0 to read in 32 values ( (8) 4-byte DMA requests driven by the FIFO empty flag) place them in A0 and compare with another value using the built in register compare. The seven bit counter manages the minor loop count of 32, while A1 holds a major loop count for tracking how many times the minor-loop executes. So far this is contained in one UDB, which is what I want, but I have an issue - once the minor loop completes, I need to hold those values so that a series of these results can then be fed out from multiple instances of this component in parallel. 

Since the local SR can only hold 8 bits (1/4th of my necessary results per buffer) it means I have to chain 4 of these in order to get my necessary storage...this essentially renders 3 additional datapath components useless - is there a way I can store the boolean outs of the compare operation into FIFO1 taking advantage of the 32 bits there and keep this component limited to a single UDB?  Even if I could store this boolean data in the FIFO bitwise can the FIFO be output to a pin in "series" or this out of the question - would I still need to take advantage of the register? 

The endstate is that I'm creating a massively parallel PWM to drive "dumb" RGB panels, but each color needs to be shifted in simultaneously since they are tied to the same clock, and there is no method for pre-writing then latching the data, like many PWM chips which have a double buffer for current data and latching in new data when it's ready...the output of the panels has to be disabled while the new data is being written, hence needing to push all 32 values at once, otherwise you see the new data shifting in and the old data shifting out. Leaving the OE low too much kills the brightness of the panels.

Any advice would be much appreciated.


user_342122993's picture
527 posts

As an idea, I suppose that it is possible to offload small amount of Datapath data to the PLD register using Verilog (basically, to make extra counter in Verilog). It will use PLD resources (not Datapath), and may still fit the UDB.


There is PSoC-VGA thread which may be of interest:'s picture
12 posts

I had seen this before and it gave me some good ideas, but I couldn't find my saved link, so thank you for sharing. 

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