What do you expect from upcoming PSoC 6 & 7 ? | Cypress Semiconductor
What do you expect from upcoming PSoC 6 & 7 ?
first, I know this is not related to PSoC 5, but since there's no general 'small talk' section in the forum, I thought this is the best place...
I've recently looked into the PSoC roadmap and there are PSoC 6 & 7 devices announced - of course without details about peripherals, etc.
So, I want to start talking about what the community expects from those new devices. Please note, I'm not affiliated to Cypress in any way, I'm just a user of their devices. I ask just because of interest.
Here are some of my points:
- capable of using SD-RAM and serial memory
- capable of using more than 16MByte
- no restrictions for bus width (e.g. currently using 16-bit memories can not handle 8-bit access)
- 32-bit bus width
- capable of serving different memory types simultanously
- capable of generating chip-select signals for configurable memory address ranges
- capable of using the address signals internally without routing them externally to GPIO input
- automatic modification of linker script memory layout
- more than six multiplexer inputs/outputs
- even more features/flexibility for UDBs (e.g. not a accumulator/data register scheme, but a four/eight/sixteen register scheme + additional FIFO buffer where each register can be used for any function)
- easier way to create customizers (would IMO help to create even more powerful user components)
- Host or OTG capability
- to be continued...
I know this is a huuuge christmas wishlist... ;) I'm curious about your wishlist.