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What are Vih/Vil for SIO input when using Vref? | Cypress Semiconductor

What are Vih/Vil for SIO input when using Vref?

Summary: 2 Replies, Latest post by Rob1 on 30 Nov 2016 05:31 AM PST
Verified Answers: 1
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pmartin_1445036's picture
2 posts

Hi there - first time poster. I'm using a 68-QFN part from the CY8C58LP family.

I would like to use P12[7] as a rising-edge triggered interrupt. This is an SIO pin whose corresponding bank voltage (VDDIO1) is 3.3V. The source driving this pin is a digital 1.8V. 

What I would like to do is use a Vref for the SIO input threshold, and configure the Vref component to Vccd (1.8V SIO Only). 

My question is - when using a Vref as an SIO input threshold, what are the relative Vih and Vil voltages?

The "Pin" component datasheet ( lists on page 31 a few Vih/Vil settings but the GPIO values listed are relative to the VDDIO voltage. If I'm using a reference voltage Vref (instead of the CMOS default), what values can I expect?

Thanks in advance -


pmartin_1445036's picture
2 posts

I think I may have answered my own question -- the "SIO Tips and Tricks in PSoC® 3 / PSoC 5LP" doc says that when using a threshold other than CMOS/LVTTL that this qualifies as differential input, and not GPIO as I thought mistakenly. So - the Vih and Vil are the SIO reference +/- 0.2V. 

So, I think what I actually want to do is set the threshold to 0.5*Vref (which would be 0.9V) and then Vil-Vih are 0.7-1.1V.

Can someone confirm?


Rob1's picture
11 posts


You are right into the pin configuration of the SIO : you can use a threshold of Vref or 0.5*Vref (it's not the case for a basic GPIO)

The Vref could be set into your TopDesign. This value can be the output of VDAC or the internal Vref 1024V.

 - Vih range : your selected threshold to VCCIO

 - Vil range : 0V to your selected threshold




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