UDBs | Cypress Semiconductor
I have established that there are 24 UDBs in the PSOC5. those UDBs can be configured using verilog. my question is: how much is the size of these UDBs (in logic gates term like in xilinx or Altera FPGAs)?? does every UDB have to be configured independently or can I just use them all at once?? so suppose I have a code that is bigger than 1 UDB, can I use 2 or more to implement it?