UDB clock source | Cypress Semiconductor
UDB clock source
I did a custom component with a State Machine that goes from one state to the next one on every rising edge of the clock input, everything run as expected using a clock component at the clk input but i would like to feed the clk using the output signal of a comparator, this seems not possible, the error suggest me to add the UDBClockEn component between the comparator output and the clk input.
I did so, connected a logic high to the enable input of the UDBClockEn and the comparator output to the ClockIn input, sadly i can clk not connect anything on the ClockOutput so i can not debug the behavior.
I remember reading somewhere that the clock signals on PSoC5LP can be provided by "any" digital signal, but i don't remember if it can be perfect %50 of duty cycle.
So my question is, any thoughts on how to solve this problem? maybe another way to generate a clk from the comparator output?
The frequency of the signal generated by the comparator output is random, that's why i would like to use it as clock source and not a proper clock component.
The project it's attached so maybe you can take a look.
Thanks in advance