UART Clarifications | Cypress Semiconductor
1. When I use buffer greater than 4 bytes, is your interrupt routine fires upon arrival of the first byte and move that byte to the RAM buffer thus applying byte-by-byte interrupt based transfer of bytes from the FIFO to the RAM?
Or, is it waiting for 4 bytes (thus stalling my program until all 4 bytes received) and operate as a 4 bytes interrupt based transfer of bytes from the FIFO to the RAM? in that case the "Byte Received interrupt" fires every 4 bytes for a long message?
2. If i want to use the On Byte Received interrupt as well, which will run first, your routine or my (please refer to both modes of using interrupts- in the interrupt C file and in the main)?
3. Please describe 5 bytes transfer delay times:
how long do i have to wait between the time the interrupt fires and the time the first byte readable in the RAM buffer? how long do i have to wait for the next byte to be ready in the RAM buffer and so on.
4. Can i create a counter which will fire an interrupt after n bytes received in the RAM buffer? (how do I wire such counter to the UART?)
5. Is there an option to create a "FIFO empty interrupt" for RX?
6. Is it possible to create UART with more than 4 bytes HW buffer (so my SW routine will not be interrupted until i want to check the buffer)?
7. Just to clear- all functions (both TX and RX) are going for the FIFO buffer in case of under 4 bytes buffer, and for the RAM buffer only (ignoring the existence of a FIFO buffer) for buffers over 4 bytes. please confirm.
Thanks in advance,