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question on datapath status interrupt

Summary: 4 Replies, Latest post by Stub for 2841092 on 22 Mar 2011 10:46 AM PDT
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Schurtz's picture
23 posts



I try to figure out the detail of datapath status register interrupt generation,  I can not find example on website.

I creat a module based on PSoC creator 213 project, in MyPWM16 module, I added cy_psoc3_statusi instance:


 cy_psoc3_statusi #(.cy_force_order(`TRUE),   .cy_md_select(7'b0000011), .cy_int_mask(7'b0000011))
  /* input [06:00] */ .status({5'b0,ce1}), // Status Bits
  /* input */              .reset(), // Reset from interconnect
  /* input */              .clock(clock), // Clock used for registering data
  /* output */            .interrupt(irq) // Interrupt signal (route to Int Ctrl)


Then Conecting the irq output  to an ISR component  (posedge trigger mode) ,

enable bit 4 of Auxiliary Control Register (0x40006490),and enable isr_1  & enable global interrupt, 

then expect isr_1 handler be entried when debugging.

But irq trigger did not happen...

-- I can not find detail information about datapath status interrupt generation, any file can be referenced?

In the other hand, I try to connnect an verilog wire to  .reset() in StatusRegi, but error happened, and information said the:

The statusi register, \MyPWM16_1:StatusRegi\, is using a routed reset which is not available in this revision of the device.

The current device does not support the routed reset feature for the statusi register. Check the selected device and switch to a newer revision that supports the feature.

--Is the reset should be left along?

--And for my concern, where I can find the correct example of datapath status register intterupt generation?



Schurtz's picture
23 posts

Btw, I  read back MyPWM16_1_StatusRegi_STATUS_REG with correct value, the low 2 bit are 0x01 / 0x03 toggled, 

MyPWM16_1_ControlReg__MASK_CTL_AUX_CTL_REG  read back correct value 0x10 as set,

MyPWM16_1_ControlReg__CONTROL_AUX_CTL_REG read back correct value 0x03 as set.

but  IRQ has not triggered. And the MSB of MyPWM16_1_StatusRegi_STATUS_REG is not toggled.


Stub for 2841092's picture
5 posts


Several things to check:

1) Make sure you are accessing the correct AUX_CTL Register. Your 2nd post said that you checked MyPWM16_1_ControlReg__MASK_CTL_AUX_CTL_REG. The correct register you need to write to to enable the interrupt output is:MyPWM16_1_StatusRegi_STATUS_AUX_CTL_REG. You might be lucky and the control register and the statusi register might share the same physical control register, but you should NOT assume it.

2) Also, the correct way to set the bit is to read /modify/write to that register. For example, create an alias to the StatusRegi like this in your .h file:

#define MyPWM16_1_Statusi_AuxCtl (* (reg8 *) MyPWM16_1_Statusi_STATUS_AUX_CTL_REG )

Then in your .c file:

MyPWM16_1_Statusi_AuxCtl |= 0x01;   /* Set bit 4 */

3) Regarding the error about the routed reset. Which revision of device are you using? If you are using an older revision, just leave the reset port disconnected and it will be fine.

 4) Your StatusRegi example code showed this port assignment to the 6 bit status bus:


But your post refers to 2 bits toggling (0x01, 0x03) in the status register when you read it, so I don't understand how this is possible. Are you certain your status bus assignment is correct?

I have some working example of using the statusi register, but the verilog looks almost exactly the same as yours. Your .md_select, .cy_int_mask parameters are correct. If you follow the example code I showed in 2) above and enable global interrupts it should work fine.



Schurtz's picture
23 posts

Great, Thanks.  It's fixed, I accessed wrong address for status_control register.

Thanks very much.

Stub for 2841092's picture
5 posts

No problem. Glad to be of help. Enjoy your datapath development adventure!

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