PWM h-bridge drive w/ output selection | Cypress Semiconductor
PWM h-bridge drive w/ output selection
I'm new to PSoC, but it looks like it might be good for my design, largely by saving a bunch of grief on routing a very small board.
My question is about the best practice for duplicating functionality that I already have: The current design uses a dsPIC, which has 4x PWM generators, with 2 pins per. The pins can be selected to be digital GPIO, or PWM output, or inverted PWM output.
I'm driving a TI DRV8833 chip, which has 2 inputs, which are connected to the 2 PWM outputs. For each direction, one of the pins is enabled, while the other is left as a digital GPIO. Switching directions then just switches which one of those output pins is enabled. Then the GPIO sets the coast/brake mode of the motor.
How should I go about mimicking this funcionality the PSoC 5? For each PWM channel, should I use a single PWM block with the pwm1 and pwm2 routed directly to output pins, and then just setting the cmp1 and cmp2 values will effectively determine which output is acting like a constant high/low GPIO, and which is PWMing?
The other wrinkle is that we are doing speed sending with a PWM holdoff (95% of the counter period), where the 95% count mark triggers the ADc conversion (differential, across motor). It looks like replicating this functionality means that I'd use one of the cmp1/cmp2 values to set this event at 0.95*period, and then use one of the pwm1/pwm2 outputs to trigger start-of-conversion on the ADC. But if I do that, then I need to figure out the output switching. Just build the output logic with 2 mux's and some logic gates?
Of course, if I could get this worked out into a whole submodule that has just a duty cycle value register, a direction bit, and a coast/brake bit, that would be super.
Any advice on this would be appreciated. We chose the previous part originally because it was a "motor control" variant, which made the described application quite straightforward.