PSOC5LP VDDIO collapsing | Cypress Semiconductor
PSOC5LP VDDIO collapsing
Before I make the experiment, maybe somebody already has an idea about this.
I'm designing an board where a PSOC5LP will be the power monitor/controller and it will also control some of the onboard ICs through SPI I2C etc etc.
Some of those ICs will be a on a power domain that can collapse or just be disabled by the PSOC it self (with all the precautions of this scenario), which will also collapse one of the VDDIO domains, where the ICs will interface the PSOC.
Will this affect proper operation on the rest of the chip? Will the PSOC power domain be robust to such scenario? I'm wandering if some ESD protection will allow some current coming from other internal power rails.
I could not find any information regarding this... My next step will be experimentation :)
Any help will be welcome,