PSoC 5 LP - 1 MSPS SAR ADC Issue | Cypress Semiconductor
PSoC 5 LP - 1 MSPS SAR ADC Issue
I recently got a -050A kit with the new PSoC 5 LP silicon. I have been trying to test the full 1 MSPS sample rate on the SAR ADCs.
The problem that occurs is that Creator tells me that I have a clocking error. At 1 MSPS, the configuration dialog tells me that I need a 18 MHz clock. What I did was to change the PLL speed to 36 MHz (2X required frequency). In the clock tree, this generates a divide by 2 clock into the ADC. Theoretically, this should work, but Creator still throws a clocking error warning.
Is there an example project that shows 1 MSPS sampling, or is this some kind of bug?