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Port Pin isr | Cypress Semiconductor

Port Pin isr

Summary: 6 Replies, Latest post by danaaknight on 28 Sep 2012 06:29 AM PDT
Verified Answers: 0
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user_228878049's picture
152 posts

 Can two isr be connected to pins of same port?? The creator was refusing to have 2 isr to pins of same port but was able to build the project with isrs on pins of different ports

user_1377889's picture
9249 posts

I have got no problems when connecting two isrs to pin 0 and 1 of port2 from a PSoC3 or PSoC5.

Will you please upload your not-working example here so that we can have a look at.



user_14586677's picture
7646 posts

The ISRs each have a distinct name ? What is the actual error dialog produced ?


Regards,. Dana.

user_78878863's picture
2551 posts

What do you want to do? Have 2 ISRs triggered from a change on the same pin? Then you either connect 2 ISRs to the same pin component, or you define one ISR and call the functionality from there.

What do you want to do exactly?

rrsh's picture
Cypress Employee
24 posts

Its possible to connect interrupt to all the pins of a port simultaneously. So i think there must be some other issue behind your problem

user_81899650's picture
19 posts

Are you trying to place two pin components with interrupt enabled on the same port? This will not be possible since each port has single ISR associated to it.

As an alternative, you can increase the number of pins in the pin component. With this, you can use the interrupt output from pin component and hook up an interrupt component to it. Only one ISR will be serviced for both pins and you will need to figure out which pin generated the interrupt within the ISR.

Second option could be hookign up isr component to the digital output of pin instead of the interrupt output. By this way you could trigger separate ISR for separate pin. Downside can be falling edge or both edge ISR will not be possible by this way.

user_14586677's picture
7646 posts

According to TRM PSOC5 can have an ISR/pin -


21.1 Features
The PSoC I/O system has these features, depending on the pin type.
■ Features supported by both GPIO and SIO:
❐ Separate I/O supplies and voltages for up to four groups of I/O
❐ Digital peripherals use DSI to connect the pins
❐ Input or output or both for CPU and DMA
❐ Eight drive modes
❐ Every pin can be an interrupt source configured as rising edge, falling edge or both edges. If required, level sensitive
interrupts are supported through the DSI
❐ Dedicated port interrupt vector for each port
❐ Slew rate controlled digital output drive mode
❐ Access port control and configuration registers on either port basis or pin basis
❐ Separate port read (PS) and write (DR) data registers to avoid read modify write errors
❐ Special functionality on a pin by pin basis

And -


All I/O pins are available for use as digital inputs and outputs for both the CPU and digital peripherals. In addition,

all I/Opins can generate an interrupt. All GPIO pins can be used for analog input, CapSense ®, and LCD segment

drive, while SIO pins are used for voltages in excess of Vdda and for programmable output voltages and input



Regards, Dana.

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